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Phase offset = m X basic clock rate (where 0 £ m < n)

The phase offset ensures that the execution of a cyclic interrupt is delayed by a certain time after the interval has expired. To avoid cyclic interrupts of different cyclic interrupt OBs being started at the same point and possibly causing a time error (cycle time exceeded) you can specify a phase offset. Refer to your "S7-300 Programmable Controller, Hardware and Installation Manual" and your "S7-400, M7-400 Programmable Controllers Module Specifications Reference Manual" for the upper limit. You can, however, assign parameters to change the default values. The default interval becomes effective when the cyclic interrupt OB assigned to it is loaded. The interval is always a whole multiple of the basic clock rate of 1 ms.Įach of the nine available cyclic interrupt OBs has a default interval (see the following table). To start a cyclic interrupt, you must specify the interval in the cyclic interrupts parameter block using STEP 7. The CPU recognizes a programming error and changes to STOP mode. If you assign parameters to deselect cyclic interrupt OBs, they can no longer be started. When you specify the intervals, make sure that there is enough time between the start events of the individual cyclic interrupts for processing the cyclic interrupts themselves. The time at which the interval starts is the mode transition from STOP to RUN. The S7 CPUs provide cyclic interrupt OBs that interrupt cyclic program processing at certain intervals.Ĭyclic interrupts are triggered at intervals.

Cyclic Interrupt Organization Blocks (OB30 to OB38) Cyclic Interrupt Organization Blocks (OB30 to OB38)